Enum faucon_asm::isa::InstructionKind[−][src]

pub enum InstructionKind {
Show 87 variants    CMPU,
    CMPS,
    CMP,
    ADD,
    ADDSP,
    CCR,
    ADC,
    SUB,
    SBB,
    SHL,
    SHR,
    SAR,
    SHLC,
    SHRC,
    NOT,
    NEG,
    HSWAP,
    SETHI,
    CLEAR,
    TEST,
    MULU,
    MULS,
    SEXT,
    AND,
    OR,
    XOR,
    XBIT,
    BSET,
    BCLR,
    BTGL,
    DIV,
    MOD,
    SETP,
    EXTR,
    EXTRS,
    INS,
    MOV,
    LD,
    ST,
    PUSH,
    POP,
    MPUSH,
    MPOP,
    MPOPADD,
    MPOPRET,
    MPOPADDRET,
    CALL,
    LCALL,
    JMP,
    BP,
    BC,
    BO,
    BS,
    BZ,
    BA,
    BNA,
    BRA,
    BNP,
    BNC,
    BNO,
    BNS,
    BNZ,
    BG,
    BLE,
    BL,
    BGE,
    LBRA,
    BCMPE,
    BCMPNE,
    RET,
    HALT,
    SLEEP,
    IMBLK,
    IMTAG,
    IMINV,
    IRET,
    TRAP,
    IMLD,
    DMLD,
    DMST,
    IMWAIT,
    DMWAIT,
    DMFENCE,
    IOWR,
    IOWRS,
    IORD,
    IORDS,
}

Expand description

Assembly instruction kinds within the Falcon v5 ISA.

The method implementations of this enum are auto-generated by a procedural derive macro from faucon-asm-derive to enable compile-time generation of opcode lookup tables.

Variants

`CMPU`

The CMPU instruction.

Compares two unsigned values and sets ALU flags based on the result.

`CMPS`

The CMPS instruction.

Compares two signed values and sets ALU flags based on the result.

`CMP`

The CMP instruction.

Compares two values and sets ALU flags based on the result.

`ADD`

The ADD instruction.

Computes the sum of two operands and stores the result.

`ADDSP`

The ADDSP instruction.

Computes the sum of the current stack pointer with a value and stores the result as the new stack pointer.

`CCR`

The CCR instruction.

Configures a DMA override for the Secure Co-Processor inside the $ccr register based on the supplied immediate value.

`ADC`

The ADC instruction.

Computes the sum of two operands with a carry and stores the result.

`SUB`

The SUB instruction.

Subtracts two operands and stores the result.

`SBB`

The SBB instruction.

Subtracts two operands with borrow and stores the result.

`SHL`

The SHL instruction.

Shifts a value left and stores the result.

`SHR`

The SHR instruction.

Shifts a value right and stores the result.

`SAR`

The SAR instruction.

Shifts a value right with sign bit and stores the result.

`SHLC`

The SHLC instruction.

Shifts a value left with carry in and stores the result.

`SHRC`

The SHRC instruction.

Shifts a value right with carry in and stores the result.

`NOT`

The NOT instruction.

Flips all bits in a value.

`NEG`

The NEG instruction.

Negates a value

`HSWAP`

The HSWAP instruction.

Rotates a value by half it’s size

`SETHI`

The SETHI instruction.

Sets the high 16 bits of a register to a value, without thouching the low 16 bits.

`CLEAR`

The CLEAR instruction.

Clears the contents of a register.

`TEST`

The TEST instruction.

Sets some flags in $csw based on the value inside the operand register.

`MULU`

THE MULU instruction.

Performs an unsigned multiplication and stores the result.

`MULS`

The MULS instruction.

Performs a signed multiplication and stores the result.

`SEXT`

The SEXT instruction.

Sign-extends a value and stores the result.

`AND`

The AND instruction.

Performs a binary AND operation on two operands.

`OR`

The OR instruction.

Performs a binary OR operation on two operands.

`XOR`

The XOR instruction.

Performs a binary XOR operation on two operands.

`XBIT`

The XBIT instruction.

Extracts a bit from a specified register and stores it in the lowest bit of the destination register, setting all other bits to 0.

`BSET`

The BSET instruction.

Sets a specific bit in a given register.

`BCLR`

The BCLR instruction.

Clears a specific bit in a given register.

`BTGL`

The BTGL instruction.

Toggles (flips) a specific bit in a given register.

`DIV`

The DIV instruction.

Performs unsigned 32-bit division on two operands.

`MOD`

The MOD instruction.

Takes the modulus of two 32-bit unsigned operands.

`SETP`

The SETP instruction.

Sets a given bit in the $flags register to the lowest bit of the source register.

`EXTR`

The EXTR instruction.

Extracts an unsigned bitfield from a supplied value.

`EXTRS`

The EXTRS instruction.

Extracts a signed bitfield from a supplied value.

`INS`

The INS instruction.

Inserts an unsigned bitfield from a source register into a destination register.

`MOV`

The MOV instruction.

Moves values of immediates or registers to other registers.

`LD`

The LD instruction.

Loads a value from Falcon DMem to a register.

`ST`

The ST instruction.

Stores a value from a register to Falcon DMem.

`PUSH`

The PUSH instruction.

Pushes a value onto the stack and increments the stack pointer by four.

`POP`

THE POP instruction.

Pops a value off the stack and increments the stack pointer by four.

`MPUSH`

The MPUSH instruction.

Pushes all registers in the range from $r0 to $rX (the supplied operand) onto the stack.

`MPOP`

The MPOP instruction.

Pops as many values off the stack as there are registers in the range from $r0 to $rX (the supplied operand).

`MPOPADD`

The MPOPADD instruction.

This instruction essentially executes a InstructionKind::MPOP and finally adds the supplied immediate value to the $sp register.

`MPOPRET`

The MPOPRET instruction.

This instruction essentially executes a InstructionKind::MPOP followed by a InstructionKind::RET.

`MPOPADDRET`

The MPOPADDRET instruction.

This instruction essentially executes a InstructionKind::MPOPADD followed by a InstructionKind::RET.

`CALL`

The CALL instruction.

Performs an unconditional call to an absolute address, pushing the return address onto the stack.

`LCALL`

The LCALL instruction.

Performs an unconditional long call to an absolute address, pushing the return address onto the stack.

`JMP`

The BRA instruction.

Performs an unconditional branch to an absolute address.

`BP`

The BP instruction.

Branches to the PC-relative target when the given predicate is true.

`BC`

The BC instruction.

Branches to the PC-relative target when the carry bit is set.

`BO`

The BO instruction.

Branches to the PC-relative target when the overflow bit is set.

`BS`

The BS instruction.

Branches to the PC-relative target when the sign bit is set.

`BZ`

The BZ instruction.

Branches to the PC-relative target when the zero bit is set.

`BA`

The BA instruction.

Branches to the PC-relative target when unsigned greater holds true.

`BNA`

The BNA instruction.

Branches to the PC-relative target when unsigned smaller or equal holds true.

`BRA`

The BRA instruction.

Branches to the PC-relative target unconditionally.

`BNP`

The BNP instruction.

Branches to the PC-relative target when the given predicate is false.

`BNC`

The BNC instruction.

Branches to the PC-relative target when the carry bit is not set.

`BNO`

The BNO instruction.

Branches to the PC-relative target when the overflow bit is not set.

`BNS`

The BNS instruction.

Branches to the PC-relative target when the sign bit is not set.

`BNZ`

The BNZ instruction.

Branches to the PC-relative target when the zero bit is not set.

`BG`

The BG instruction.

Branches to the PC-relative target when signed greater holds true.

`BLE`

The BLE instruction.

Branches to the PC-relative target when signed less or equal holds true.

`BL`

The BL instruction.

Branches to the PC-relative target when signed less holds true.

`BGE`

The BGE instruction.

Branches to the PC-relative target when signed greater or equal holds true.

`LBRA`

The LBRA instruction.

Performs an unconditional long branch to an absolute address.

`BCMPE`

The BCMPE instruction.

Performs a conditional branch to a PC-relative address if the value of the register operand matches the second immediate operand.

`BCMPNE`

The BCMPNE instruction.

Performs a conditional branch to a PC-relative address if the value of the register operand does not match the second immediate operand.

`RET`

The RET instruction.

Returns from a previous subroutine call.

`HALT`

The HALT instruction.

Halts microcode execution and triggers the exit interrupt so that the processor can only be restarted by the host machine.

`SLEEP`

The SLEEP instruction.

Puts the processor into sleep state until an unmasked interrupt is received. Repeated until the given flag bit is cleared.

`IMBLK`

The IMBLK instruction.

Loads the TLB that covers a given physical page into a destination register.

`IMTAG`

The IMTAG instruction.

Loads the TLB that covers a given virtual address into a destination register.

`IMINV`

The IMINV instruction.

Invalidates a non-secret TLB entry corresponding to a specified physical page.

`IRET`

The IRET instruction.

Returns from an interrupt handler.

`TRAP`

The TRAP instruction.

Triggers a software trap.

`IMLD`

The IMLD instruction.

Submits a DMA transfer request to load code from external memory.

`DMLD`

The DMLD instruction.

Submits a DMA transfer request to load data from external memory.

`DMST`

The DMST instruction.

Submits a DMA transfer request to store local Falcon data in external memory.

`IMWAIT`

The IMWAIT instruction.

Waits for all DMA code load transfers to complete.

`DMWAIT`

The DMWAIT instruction.

Waits for all DMA data load/store transfers to complete.

`DMFENCE`

The DMFENCE instruction.

Constructs a memory barrier for DMA data transfers, ensuring that all transfers queried prior to constructing the barrier will be finished before the ones after it.

`IOWR`

The IOWR instruction.

Asynchronously writes a word to the I/O space of the microprocessor.

`IOWRS`

The IOWRS instruction.

Synchronously writes a word to the I/O space of the microprocessor.

`IORD`

The IORD instruction.

Asynchronously reads a word from the I/O space of the microprocessor.

`IORDS`

The IORDS instruction.

Synchronously reads a word from the I/O space of the microprocessor.